Element isolation trenches formed by embedding an insulating film, such as a silicon oxide film, into grooves or trenches defined in a semiconductor substrate have excellent advantages as compared with a field insulating film formed by a conventional selective oxidation (Local Oxidation of Silicon; LOCOS) method. Such element isolation trenches are advantageous even over the ensuring of sub-threshold characteristics, and reductions in junction leaks and backgate effects, in that (a) element isolation intervals can be reduced, (b) control of element isolation film-thickness is easy and a field reversal voltage is easy to set, and (c) an impurity is implanted in the side walls and bottom in each trench in parts to thereby allow separation of an inversion-preventing layer from a diffused layer and a channel region for each element.
In order to define element isolation trenches in a semiconductor substrate (hereinafter referred to simply as a “substrate”), for example, the substrate is first etched with a silicon nitride film as a mask to thereby define grooves or trenches in the substrate in an element isolation region. Subsequently, a method is employed of depositing a silicon oxide film on the substrate so as to embed the silicon oxide inside the trenches, and, thereafter, the unnecessary silicon oxide film lying outside each trench is removed by chemical mechanical polishing (CMP). This type of technology has been described in, for example, 1997 Symposium on VLSI Tech. Digest of Tech. Papers pp. 121-122.
However, a problem has been pointed out in that a phenomenon (called “kink characteristic or hump characteristic”, for example) occurs, such that, when a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on (i.e., insulatedly on) the substrate with the element isolation trenches defined therein by using the above-described method, the threshold voltage (Vth) is locally reduced at an end of an active region brought into contact with each element isolation trench, and a channel is inverted at a low gate voltage (Vg) to thereby allow a drain current to flow.
The reduction in threshold voltage is considered to result from the fact that, for example, some of an impurity for threshold voltage control, which has been introduced into the substrate in the active region, is diffused into the silicon oxide film in each element isolation trench by in-manufacturing process heat treatment to thereby reduce the concentration of the impurity at each end of the active region, and the thickness of a gate insulator formed at each end of the active region becomes thin due to a reduction (recess) in the thickness of the silicon oxide film at the end of each element isolation trench, which occurs during the manufacturing process, whereby a high electric field concentrates on the thickness-reduced gate insulator.
Japanese Patent Application Laid-Open No. Hei 8-55985, showing Japanese Patent Application Publication corresponding to U.S. Pat. No. 5,567,553, discloses a technology in which, as a countermeasure against the problem that a leakage current increases in a cut-off region due to a reduction in threshold voltage, which is developed at an end of an active region, the gate length (channel length) of a gate electrode in a region, which crosses the boundary between the active region and each element isolation trench, is set longer than the gate length thereof in a central portion of the active region, whereby the threshold voltage at the end of the active region is set to substantially the same value as the threshold voltage in the central portion of the active region.
The article entitled “Anomalous Gate Length Dependence of Threshold Voltage of Trench-Isolated Metal Oxide Semiconductor Field Effect Transistor” (T. Oishi, K. Shiozawa, A. Furukawa, Y. Abe and Y. Tokuda, JJAP 37(1998) L852-L854) has discussed the influence of the concentration of an electric field on an end of an active region upon gate length dependence of a threshold voltage, using a gate electrode (I type gate) having a linear pattern and a gate electrode (H type gate) in which branch patterns extending in a direction orthogonal to the linear pattern are provided at both ends of the linear pattern and in which the linear pattern does not cross the boundary between the active region and each element isolation trench.